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low input offset, high slew rate, wide bandwidth, jfet input operational amplifiers the mc33282/284 series of high performance operational amplifiers are quality fabricated with innovative bipolar and jfet design concepts. this dual and quad amplifier series incorporates jfet inputs along with a patented zip r trim ? element for input offset voltage reduction. these devices exhibit low input offset voltage, low input bias current, high gain bandwidth and high slew rate. dualdoublet frequency compensation is incorporated to produce high quality phase/gain performance. in addition, the mc33282/284 series exhibit low input noise characteristics for jfet input amplifiers. its all npn output stage exhibits no deadband crossover distortion and a large output voltage swing. they also provide a low open loop high frequency output impedance with symmetrical source and sink ac frequency performance. the mc33282/284 series are specified over 40 to +85 c and are available in plastic dip and soic surface mount packages. ? low input offset voltage: trimmed to 200 m v ? low input bias current: 30 pa ? low input offset current: 6.0 pa ? high input resistance: 10 12 w ? low noise: 18 nv hz ? ?? ??? ? high gain bandwidth products: 35 mhz @ 100 khz ? high slew rate: 15 v/ m s ? power bandwidth: 175 khz ? unity gain stable: w/capacitance loads to 300 pf ? large output voltage swing: +14.1 v/14.6 v ? low total harmonic distortion: 0.003% ? power supply drain current: 2.15 ma per amplifier ? dual supply operation: 2.5 v to 18 v (max) ordering information op amp function device operating temperature range package dual mc33282d sop8 dual mc33282p t 40 to +85 c plastic dip quad mc33284d t a = 40 to +85 c so14 quad mc33284p plastic dip on semiconductor ? semiconductor components industries, llc, 2002 march, 2002 rev. 1 1 publication order number: mc33282/d mc33282 mc33284 semiconductor technical data high performance operational amplifiers p suffix plastic package case 626 d suffix plastic package case 751 (so8) output 1 inputs 1 v ee v cc output 2 inputs 2 1 2 3 45 6 7 8 - + 1 - + 2 (top view) dual pin connections 1 8 1 8 p suffix plastic package case 646 d suffix plastic package case 751a (so14) (top view) output 1 inputs 1 v cc inputs 2 output 2 output 4 inputs 4 v ee inputs 3 output 3 - + 1 - + 4 + - 2 + - 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 quad pin connections 14 1 14 1
mc33282 mc33284 http://onsemi.com 2 maximum ratings rating symbol value unit supply voltage (v cc to v ee ) v s +36 v input differential voltage range v idr (note 1) v input voltage range v ir (note 1) v output short circuit duration (note 2) t sc indefinite sec maximum junction temperature t j +150 c storage temperature t stg 60 to +150 c maximum power dissipation p d (note 2) mw notes: 1. either or both input voltages should not exceed v cc or v ee . 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded (see figure 2). dc electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol figure min typ max unit input offset voltage (r s = 10 w , v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c |v io | 3 e e 0.2 e 2.0 4.0 mv average temperature coefficient of input offset voltage r s = 10 w , v cm = 0 v, v o = 0 v, t a = t low to t high | d v io |/ d t 3 e 15 e m v/ c input bias current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c i ib 4, 5 200 2.0 30 e 200 2.0 pa na input offset current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c i io 100 1.0 6.0 e 100 1.0 pa na common mode input voltage range ( d v io = 5.0 mv, v o = 0 v) v icr 6 11 e 12 +14 e +11 v large signal voltage gain (v o = 10 v, r l = 2.0 k w ) t a = +25 c t a = 40 to +85 c a vol 7 50 25 200 e e e v/mv output voltage swing (v id = 1.0 v) r l = 2.0 k w r l = 2.0 k w r l = 10 k w r l = 10 k w v o + v o v o + v o 8, 9, 10 13.2 e 13.7 e +13.7 13.9 +14.1 14.6 e 13.2 e 14.3 v common mode rejection (v in = 11 v) cmr 11 70 90 e db power supply rejection v cc /v ee = +15 v/15 v, +5.0 v/15 v, +15 v/5.0 v psr 12 75 100 e db output short circuit current (v id = 1.0 v, output to ground) source sink i sc 13, 14 15 e +21 27 e 15 ma power supply current (v o = 0 v, per amplifier) t a = +25 c t a = 40 to +85 c i d 15 e e 2.15 e 2.75 3.0 ma
mc33282 mc33284 http://onsemi.com 3 ac electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol figure min typ unit slew rate (v in = 10 v to +10 v, r l = 2.0 k w , c l = 100 pf, a v = +1.0) sr 16, 28, 29 8.0 15 v/ m s gain bandwidth product (f = 100 khz) gbw 17 20 35 mhz ac voltage gain (r l = 2.0 k w , v o = 0 v, f = 20 khz) a vo 18, 21 e 1750 v/v unity gain frequency (open loop) f u e 5.5 mhz gain margin (r l = 2.0 k w , c l = 0 pf) a m 19, 20 e 15 db phase margin (r l = 2.0 k w , c l = 0 pf) f m 19, 20 e 40 degrees channel separation (f = 20 hz to 20 khz) cs 22 e 120 db power bandwidth (v o = 20 v pp , r l = 2.0 k w , thd 1.0%) bw p e 175 khz distortion (r l = 2.0 k w , f = 20 hz to 20 khz, v o = 3.0 v rms , a v = +1.0) thd 23 e 0.003 % open loop output impedance (v o = 0 v, f = 9.0 mhz) |z o | 24 e 37 w differential input resistance (v cm = 0 v) r in e 10 12 w differential input capacitance (v cm = 0 v) c in e 5.0 pf equivalent input noise voltage (r s = 100 w , f = 1.0 khz) e n 25 e 18 nv/ hz equivalent input noise current (f = 1.0 khz) i n e 0.01 pa/ hz d 1 r 2 r 3 r 6 r 10 r 13 q 8 j 3 c 1 d 2 v in j 2 q 5 q 11 q 9 j 1 z 1 q 1 q 2 q 3 r 1 c 2 v ee r 13 r 15 r 12 r 5 r 4 q 6 q 7 q 10 q 12 q 13 c 6 c 5 c 4 j 5 v in j 4 d 3 q 15 v cc v o q 17 q 18 d 5 q 14 q 16 r 17 d 4 q 4 ab c d c 3 r 8 r 16 + figure 1. equivalent circuit schematic (each amplifier)
mc33282 mc33284 http://onsemi.com 4 figure 2. maximum power dissipation versus temperature figure 3. input offset voltage versus temperature for typical units figure 4. input bias current versus temperature figure 5. input bias current versus common mode voltage figure 6. input common mode voltage range versus temperature figure 7. open loop voltage gain versus temperature p d (max), maximum power dissipation (mw) -60 -40 -20 0 20 40 60 80 100 120 140 160 180 mc33282p & mc33284p mc33284d mc33282d t a , ambient temperature ( c) t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 v io , input offset voltage (mv) v cc =+15 v v ee =-15 v r s = 10 w v cm = 0 v unit 1 unit 2 unit 3 unit 1 unit 2 unit 3 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) v cc , v ee = 2.5 v v cc , v ee = 15 v i ib , input bias current (pa) -15 -12 -9.0 -6.0 -3.0 0 3.0 6.0 9.0 12 15 v cm , common mode voltage (v) i ib , input bias current (pa) v cc =+15 v v ee =-15 v t a = 25 c v icr , input common mode voltage range (v) t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 v cc =+5.0 v to +18 v v ee =-5.0 v to -18 v d v io = 5.0 mv v o = 0 v a vol , open loop voltage gain (db) -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) 2400 2000 1600 1200 800 400 0 5.0 3.0 1.0 -1.0 -3.0 -5.0 400 350 300 250 200 150 100 50 0 600 500 400 300 200 100 0 v cc v cc -0.5 v v cc -1.0 v v cc -1.5 v v ee+ 1.5 v v ee +1.0 v v ee +0.5 v v ee 150 140 130 120 110 100 v cc =+15 v v ee =-15v r l = 2.0 k w f = 10 hz d v o = 10 v to +10 v
mc33282 mc33284 http://onsemi.com 5 v o , output voltage (v ) pp v o , output voltage (v ) pp mmni mmm figure 8. output voltage swing versus supply voltage figure 9. output voltage versus frequency figure 10. output saturation voltage versus load current figure 11. common mode rejection versus frequency figure 12. positive power supply rejection versus frequency figure 13. output short circuit source current versus temperature v cc , v ee supply voltage (v) 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 t a =25 c r l =10 k r l =2.0 k 1.0 k 10 k 100 k 1.0 m v cc =+15 v v ee =-15 v r l = 2.0 k w a v = +1.0 thd = 1.0% t a = 25 c f, frequency (hz) v sat , output saturation voltage (v) 2.0 4.0 6.0 8.0 14 16 18 20 t a =+25 c t a =125 c t a =-55 c t a =-55 c i l , load current (ma) v cc = +15 v r l to gnd v ee =-15 v cmr, common mode rejection (db) 10 100 1.0 k 10 k 100 k 1.0 m f, frequency (hz) v cc =+15 v v ee =-15 v v cm =0 v d v cm = 1.5 v +psr, power supply rejection (db) 10 100 1.0 k 10 k 100 k 1.0 m f, frequency (hz) v cc =+15 v v ee =-15 v d v cc = 1.5 v t a = 25 c psr- psr+ |i sc |, output short circuit current (ma) -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) v cc , v ee = 2.5 v v cc , v ee = 15 v v id = 1.0 v r l < 100 w 10 12 40 36 32 28 24 20 16 12 8.0 4.0 0 30 27 24 21 18 15 12 9.0 6.0 3.0 0 v cc -4.0 v v cc v cc -8.0 v v cc -12 v v ee +4.0 v v ee +2.0 v v ee 120 100 80 60 40 20 0 120 100 80 60 40 20 0 50 45 40 35 30 25 20 15 10 5.0 0 +psr=20lo g - + a dm d v o v ee v cc d v o /a dm d v cc t a =125 c t a =+25 c d v cm d v o cmr=20log mvmni mmm xmi d v cm d v o x a dm - + a dm
mc33282 mc33284 http://onsemi.com 6 figure 14. output short circuit sink current versus temperature figure 15. power supply current versus supply voltage figure 16. slew rate versus temperature figure 17. gain bandwidth product versus temperature figure 18. gain and phase versus frequency figure 19. phase margin and gain margin versus differential source resistance |i sc |, output short circuit current (ma) -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) v cc , v ee = 15 v v cc , v ee = 2.5 v v id = 1.0 v r l < 100 w i d , power supply current (ma) -55 -25 0 25 50 75 100 125 v cc , v ee = 15 v v cc , v ee = 2.5 v t a , ambient temperature ( c) sr, slew rate (v/ m s) -55 -25 0 25 50 75 100 125 v cc =+15 v v ee =-15 v d v in =20 v c l =100 pf r l =2.0 k w noninverting amplifier inverting amplifier gbw, gain bandwidth product (mhz) -55 -25 0 25 50 75 100 125 v cc =+15 v v ee =-15 v f=100 khz r l = 2 k w c l = 0 pf t a , ambient temperature ( c) t a , ambient temperature ( c) a v , voltage gain (db) 10 m 100 m f , phase (degrees) t a =25 c c l =0 pf 1a 2a 1b 1a) phase v cc =18 v, v ee =-18 v 2a) phase v cc =1.5 v, v ee =-1.5 v 1b) gain v cc =18 v, v ee =-18 v 2b) gain v cc =1.5 v, v ee =-1.5 v f, frequency (hz) 1.0 m 100k a m , gain margin (db) 10 100 1.0 k 10 k f m , phase margin ( degrees ) v cc =+15 v v ee =-15 v r t =r 1 +r 2 v o =0 v t a =25 c phase margin gain margin r t , differential source resistance ( w ) 2b 50 45 40 35 30 25 20 15 10 5.0 0 3.0 2.5 2.0 1.5 1.0 0.5 0 16 14 12 10 8.0 6.0 4.0 2.0 0 50 40 30 20 10 0 50 40 30 20 10 0 -10 -20 -30 -40 -50 20 16 12 8.0 4.0 0 80 100 120 140 160 180 200 220 240 50 40 30 20 10 0 260 r 1 r 2 v in v o + -
mc33282 mc33284 http://onsemi.com 7 drive channel v cc =+15 v v ee =-15 v r l = 2.0 k w d v od = 20 v pp t a = 25 c figure 20. open loop gain and phase margin versus output load capacitance figure 21. gain and phase versus frequency figure 22. channel separation versus frequency figure 23. total harmonic distortion versus frequency figure 24. output impedance versus frequency figure 25. input referred noise voltage versus frequency a m , open loop gain margin (db) 10 50 100 500 1.0 k f m , phase margin (degrees) c l , output load capacitance (pf) v in + - 2.0 k w v o c l phase margin gain margin v cc =+15 v v ee =-15 v v o =0 v 10 m 100 m f , phase ( degrees ) f, frequency (hz) 1.0 m 100k a v , voltage gain (db) 1a 2a phase gain 1b 2b t a =25 c c l =0 pf 1a) phase, v o =10 v 2a) phase, v o =-10 v 1b) gain, v o =10 v 2b) gain, v o =-10 v cs, channel separation (db) 100 1.0 k 10 k 100 k 1.0 m f, frequency (hz) thd, total harmonic distortion (%) 10 100 1.0 k 10 k 100 k a v =+1000 v cc =+15v v ee =-15v v o =2 vpp t a =25 c a v =+100 a v =+10 a v =+1.0 f, frequency (hz) |z o |, output impedance ( w ) 10 k 100 k 1.0 m 10 m v cc =+15 v v ee =-15 v v o =0 v t a =25 c a v =100 a v =10 a v =1000 a v =1.0 10 k 100 k 10 100 1.0 k e , input referred noise voltage (nv/ n f, frequency (hz) v cc = +15 v v ee = -15 v t a = 25 c hz) v cc =15 v v ee =-15 v f, frequency (hz) 12 10 8.0 6.0 4.0 2.0 0 50 40 30 20 10 0 -10 -20 -30 -40 -50 160 150 140 130 120 110 100 1.0 0.1 0.01 0.001 100 90 80 70 60 50 40 30 20 10 0 50 30 20 10 0 40 0 10 20 30 40 50 60 80 100 120 140 160 180 200 220 240 - + 200 200 2.0k v o input noise voltage test circuit
mc33282 mc33284 http://onsemi.com 8 10 figure 26. percent overshoot versus load capacitance figure 27. noninverting amplifier overshoot figure 28. noninverting amplifier slew rate figure 29. inverting amplifier slew rate 1.0 k 10 100 100 80 70 60 50 20 40 30 0 90 c l , load capacitance (pf) percent overshoot (%) v cc = +15 v v ee = -15 v r l = 2.0 k t a = 25 c t, time (1.0 m s/div) v o , output voltage (5.0 v/div) v o , output voltage (50 mv/div) v o , output voltage (5.0 v/div) t, time (1.0 m s/div) t, time (1.0 m s/div)
mc33282 mc33284 http://onsemi.com 9 p suffix plastic package case 62605 issue k d suffix plastic package case 75105 (so8) issue r outline dimensions notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 seating plane 1 4 5 8 a 0.25 m cb ss 0.25 m b m h c x 45 l dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.18 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0 7 l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeters. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include mold protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d e h a b e b a1 c a 0.10
mc33282 mc33284 http://onsemi.com 10 p suffix plastic package case 64606 issue l d suffix plastic package case 751a03 (so14) issue f outline dimensions notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f hg d k c n l j m seating plane dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.300 bsc 7.62 bsc m 0 10 0 10 n 0.015 0.039 0.39 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc33282 mc33284 http://onsemi.com 11 notes
mc33282 mc33284 http://onsemi.com 12 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33282/d zip r trim is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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